# ECET 230 ECET230 ECET/230 ENTIRE COURSE HELP – DEVRY UNIVERSITY

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## ECET 230 ECET230 ECET/230 ENTIRE COURSE HELP – DEVRY UNIVERSITY

ECET 230 Week 1 Homework

ECET 230 Week 2 Homework

ECET 230 Week 1 iLab Introduction to Quartus II, VHDL, and the FPGA Board

ECET 230 Week 2 iLab Decoders and Multiplexers

ECET 230 Week 3 Homework

ECET 230 Week 3 iLab Flip-Flops in VHDL

ECET 230 Week 4 Homework

ECET 230 Week 4 iLab Introduction to Flip-Flops

ECET 230 Week 5 Homework

ECET 230 Week 5 iLab Design of Synchronous Counters

ECET 230 Week 6 Homework

ECET 230 Week 6 iLab Design of a Simple State Machine

ECET 230 Week 7 Homework

ECET 230 Week 7 iLab Traffic Light Design Program

### Description

## ECET 230 ECET230 ECET/230 ENTIRE COURSE HELP – DEVRY UNIVERSITY

ECET 230 Week 1 Homework

ECET 230 Week 2 Homework

ECET 230 Week 1 iLab Introduction to Quartus II, VHDL, and the FPGA Board

ECET 230 Week 2 iLab Decoders and Multiplexers

ECET 230 Week 3 Homework

ECET 230 Week 3 iLab Flip-Flops in VHDL

ECET 230 Week 4 Homework

ECET 230 Week 4 iLab Introduction to Flip-Flops

ECET 230 Week 5 Homework

ECET 230 Week 5 iLab Design of Synchronous Counters

ECET 230 Week 6 Homework

ECET 230 Week 6 iLab Design of a Simple State Machine

ECET 230 Week 7 Homework

ECET 230 Week 7 iLab Traffic Light Design Program

## ECET 230 ECET230 ECET/230 ENTIRE COURSE HELP – DEVRY UNIVERSITY

**ECET 230 Week 1 Homework**

1. Develop the Boolean equation for the circuit shown below

2. Determine the output Y in Problem 1 for the input values shown below

3. Redraw the circuit in Problem 1 using only 2-input NAND gates

4.Develop the Boolean equation for the circuit shown below

5.Determine the period of a clock waveform whose frequency is:

6.Write the VHDL text file (Entity and Architecture) for a 2-input NAND gate.

7. Write the VHDL text file for a 3-input NOR gate.

8.Write the VHDL text file for the circuit shown below

9.Develop the look-up-table (LUT) for the circuit shown in Problem 8.

10. Develop the look-up table for the Boolean equation:

## ECET 230 ECET230 ECET/230 ENTIRE COURSE HELP – DEVRY UNIVERSITY

**ECET 230 Week 2 Homework**

1. When a HIGH is on the output of the decoding circuit below, what is the binary code appearing on the inputs?

2. Write the Boolean equations for each of the following codes if an active-LOW decoder output is required:

3. Write the VHDL text file for a 3-to-8 decoder.

4. A 7-segment decoder/driver drives the display below. Using the waveforms shown, determine the sequence of digits that appear on the display.

5. Construct a truth table for an active-LOW output BCD (1-of-10) decoder

6. Derive the truth table for the Y output in the diagram below.

7. Derive the Boolean equation for the Y output in Problem

8.For the multiplexer shown below, determine the output for the following input state:

9. Determine the function of the circuit shown below.

10. Write the VHDL text file for the circuit shown in Problem 9

## ECET 230 ECET230 ECET/230 ENTIRE COURSE HELP – DEVRY UNIVERSITY

**ECET 230 Week 1 iLab Introduction to Quartus II, VHDL, and the FPGA Board**

*Objectives:*

1.Learn How to write basic logic circuits using VHDL.

2.Using Quartus II compile and simulate the text file and then analyze the simulation for proper operation.

3.Learn how to assign pins and then how to download the program to the eSOC II board.

4. Verify that the eSOC II board behaves correctly when the output is what is expected depending on the input configuration.

Using the results of the compilation for the Design Project, what percent of the FPGA is used to implement the design.

In the compilation process, what is the difference between an error and a warning?

Use the zoom tool to measure the propagation delays, t_{PHL} and t_{PLH}, for the FPGA implementing the Design Project (the times between an input change of state and the subsequent output change of state in response). The zoom tool is used by expanding the time scale, right clicking on one signal and selecting “Insert Time Bar.”

What is “JTAG” and why is it used? Be sure to cite your sources.

## ECET 230 ECET230 ECET/230 ENTIRE COURSE HELP – DEVRY UNIVERSITY

**ECET 230 Week 2 iLab Decoders and Multiplexers**

* Objectives:* Discover the operation of 7-segment displays, BCD-to-7-semgment decoders, multiplexers and demultiplexers. Demonstrate the simulation of a discrete DEMUX and decode operation with discrete components. Construct a discrete circuit with these components. Use VHDL to emulate this circuit within an FPGA.

Why are the 330 Ω resistors required for the discrete logic circuit, but not for the MultiSim simulated circuit or the eSOC III circuit?

Create a partial truth table showing the requirements for a seven-segment decoder to output a hexadecimal digit. This requires four input bits and six output states, A – F. For each output state, show the segments a-g. The output states for the inputs 0 – 9 are the same as for the 74LS47 (see focus.ti.com). Use capital letters A, C, E, F and lower case for b and d.

Why is the seven-segment display driven with an active-LOW signal using discrete logic and an active-HIGH with the eSOC board?