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ECEN 248 ECEN248 Lab 12 post lab – Texas A&M

Lab 12: The Traffic Light Controller Lab

OBJECTIVES:

Lab twelve was focused on implementing all of the previous labs together as well as introducing the Mealy state machine, which is just another form of the Moore state machine.

The goal was to create a traffic light intersection. The lights were on a timing schedule and the red, green, and yellow lights were described through a Mealy state machine.

DESIGN: Modified state diagram of the Traffic Light Controller.

Below is the source code for the first and second experiments.
//traffic light controller fsm
`timescale 1ns/1ps
`default_nettype none
`define one_sec 50000000
`define three_sec 150000000
`define thirty_sec 1500000000
`define fifteen_sec 750000000
module tlc_fsm_exp1(
output reg [2:0] state,//
output for debugging
output reg RstCount,//use an always blockoutput reg [1:0] highwaySignal, farmSignal,
input wire [30:0] Count,//use n computed earlier
input wire Clk, Rst//clock and reset);
//defining statesparameter
Srst = 3’b110,
S0 = 3’b000,
S1 = 3’b001,
S2 = 3’b010,
S3 = 3’b011,
S4 = 3’b100,
S5 = 3’b101;
//defining colorsparameter
green = 2’b00,
yellow = 2’b01,
red= 2’b10;//intermediate netsreg [2:0] nextState;//next state logicalways@(state or Count)case(state)Srst: nextState = S0;S0: beginif(Count == `one_sec)//if count reachednextState = S1;//transitionelse //otherwisenextState = S0;//remain in current stateendS1: beginif(Count == `thirty_sec)//if count reachednextState = S2;//transitionelse //otherwisenextState = S1;//remain in current stateendS2: beginif(Count == `three_sec)//if count is reachednextState = S3;//transitionelse
nextState = S2;//remain in current stateendS3: beginif(Count == `one_sec)//if count is reachednextState = S4;//transitionelsenextState = S3;//remain in current stateendS4: beginif(Count == `fifteen_sec)//if count is reachednextState = S5;//transitionelsenextState = S4;//remain in current stateendS5: beginif(Count == `three_sec)//if count reachednextState = S0;//transitionelse//otherwisenextState = S5;//remain in current stateenddefault://avoid latchesnextState = Srst;endcase/*describe output logic*/always@(state or Count)case(state)Srst : beginhighwaySignal = red;farmSignal= red;RstCount = 1;endS0: beginhighwaySignal = red;farmSignal= red;if(Count == `one_sec)//if count reachedRstCount = 1;//reset counterelse//otherwiseRstCount = 0;//let counter runendS1: begin
highwaySignal = green;farmSignal= red;if(Count == `thirty_sec)//if count reachedRstCount = 1;//reset counterelse//otherwise

ECEN 248 ECEN248 Lab 12 post lab – Texas A&M

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ECEN 248 – Spring 2016 Register Now PreLab 10.pdf Textbook Exercises Fundamentals of Digital Logic with VHDL Design image Fundamentals of Digital Logic with VHDL Design Ch 2, Section EoC End of Chapter, Exercise 2.1Consider the expression x+yz=(x+y)(x+z) .

Consider the left handed term is x+yz and the right…Fundamentals of Digital Logic with VHDL Design Ch 3, Section EoC End of Chapter, Exercise 3.1For a 3 input logic circuit, there are 8 different combinations for which the output can be…

ECEN 248 ECEN248 Lab 12 post lab – Texas A&M

Fundamentals of Digital Logic with VHDL Design Ch 4, Section EoC End of Chapter, Exercise 4.1Write the truth table for the given function f(x_1,x_2,x_3)=\sum m(1,2,3,5) . Determine the number…Fundamentals of Digital Logic with VHDL Design Ch 5, Section EoC End of Chapter, Exercise 5.1

All positive numbers are called unsigned numbers. The binary number is represented by using the…Fundamentals of Digital Logic with VHDL Design Ch 6, Section EoC End of Chapter, Exercise 6.1Draw a 3 to 8 binary decoder for the given function, f(w_1, w_2, w_3)=\sum m(0, 2, 3, 4, 5, 7) .

It…Fundamentals of Digital Logic with VHDL Design Ch 7, Section EoC End of Chapter, Exercise 7.5Consider the characteristic table of D flip-flop is shown in Table 1. …Fundamentals of Digital Logic with VHDL Design Ch 8, Section EoC End of Chapter, Exercise 8.4The inputs are clock and reset.

The output is z and it consists of 4 bits. According to the states…Fundamentals of Digital Logic with VHDL Design Ch 9, Section EoC End of Chapter, Exercise 9.1Consider that w_{1} and w_{2} are the inputs, y_{1} and y_{2} are the next states, z_{1} and z_{2}…

Fundamentals of Digital Logic with VHDL Design Ch 10, Section EoC End of Chapter, Exercise 10.1The modified shift register circuit in which the parallel-load operation can be performed only when…Fundamentals of Digital Logic with VHDL Design INTRO TO DIGITAL LOGIC

ECEN 248 ECEN248 Lab 12 post lab – Texas A&M

Tests Questions & Answers Showing 1 to 8 of 26 View all Please see attachments for details 1 2 3 4 5 Please see an attachment for details 1 2 3 4 5 Please see an attachment for details 1 2 3 4 5

Please see an attachment for details 1 2 3 4 5 The attached problems please 1 2 3 4 5 The three attached problems. 1 2 3 4 5 These are simplified equations using boolean algebra can you please help me optimize each one and draw the circuits please. 1 2 3 4 5 Can you please help me simplify each one separately using boolean algebra 1 2 3 4 5

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