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ECEN 248 ECEN248 Lab 8 Introduction to Sequential Logic – Texas A&M

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ECEN 248 ECEN248 Lab 8 Introduction to Sequential Logic – Texas A&M

Lab 8: Introduction to Sequential Logic

Objectives:

In this lab, I will be introduced to sequential logic circuits. Within the circuits, I will learn about latches, flip-flops, and adding time delays to circuits.

Before now we have not paid attention to time delays but now I will account for timing with a clock signal. I also will also be using technical latches for the first time which include a clock and a master-slave layout of the flip-flopcircuit.

Design:

Description

  

ECEN 248 ECEN248 Lab 8 Introduction to Sequential Logic – Texas A&M

Lab 8: Introduction to Sequential Logic

Objectives:

In this lab, I will be introduced to sequential logic circuits. Within the circuits, I will learn about latches, flip-flops, and adding time delays to circuits.

Before now we have not paid attention to time delays but now I will account for timing with a clock signal. I also will also be using technical latches for the first time which include a clock and a master-slave layout of the flip-flopcircuit.

Design:

During the lab, I had to create an SR-latch, D-latch, D flip-flop, a behavioral D-latch, behavioral D flip-flop, and a 2-bit synchronous adder using Verilog. I also had to modify test bench codes inorder to test all inputs. Listed below are all by source codes from this lab with comments.

sr_latch

`timescale 1ns/1psmodule sr_latch(Q, notQ, En, S, R);//declare all portsoutput wire Q, notQ;input wire En, S, R;//intermediate nets//nandSEN is the output of NAND(S,EN)//nandREN is the output of NAND(R,EN)wire nandSEN, nandREN;//delay of nand0 is 2ns.

nand #2 nand0(Q, nandSEN, notQ);

nand #2 nand1(notQ, nandREN, Q);

nand #2 nand2(nandSEN, S, En);

nand #2 nand3(nandREN, R, En);endmodule

sr_latch with 4 delay

`timescale 1ns/1psmodule sr_latch(Q, notQ, En, S, R);//declare all portsoutput wire Q, notQ;input wire En, S, R;//intermediate nets//nandSEN is the output of NAND(S,EN)//nandREN is the output of NAND(R,EN)wire nandSEN, nandREN;//delay of nand0 is 2ns.nand

#4 nand0(Q, nandSEN, notQ);nand

#4 nand1(notQ, nandREN, Q);

nand #4 nand2(nandSEN, S, En);

nand #4 nand3(nandREN, R, En);endmodule

d_latch

`timescale 1ns/ 1ps`default_nettype nonemodule d_latch(Q, notQ, En, D);//i/o wiresoutput wire Q, notQ;

ECEN 248 ECEN248 Lab 8 Introduction to Sequential Logic – Texas A&M

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ECEN 248 ECEN248 Lab 8 Introduction to Sequential Logic – Texas A&M

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ECEN 248 – Spring 2016 Register Now PreLab 10.pdf Textbook Exercises Fundamentals of Digital Logic with VHDL Design image Fundamentals of Digital Logic with VHDL Design Ch 2, Section EoC End of Chapter, Exercise 2.1Consider the expression x+yz=(x+y)(x+z) .

Consider the left handed term is x+yz and the right…Fundamentals of Digital Logic with VHDL Design Ch 3, Section EoC End of Chapter, Exercise 3.1For a 3 input logic circuit, there are 8 different combinations for which the output can be…

ECEN 248 ECEN248 Lab 8 Introduction to Sequential Logic – Texas A&M

Fundamentals of Digital Logic with VHDL Design Ch 4, Section EoC End of Chapter, Exercise 4.1Write the truth table for the given function f(x_1,x_2,x_3)=\sum m(1,2,3,5) . Determine the number…Fundamentals of Digital Logic with VHDL Design Ch 5, Section EoC End of Chapter, Exercise 5.1

All positive numbers are called unsigned numbers. The binary number is represented by using the…Fundamentals of Digital Logic with VHDL Design Ch 6, Section EoC End of Chapter, Exercise 6.1Draw a 3 to 8 binary decoder for the given function, f(w_1, w_2, w_3)=\sum m(0, 2, 3, 4, 5, 7) .

It…Fundamentals of Digital Logic with VHDL Design Ch 7, Section EoC End of Chapter, Exercise 7.5Consider the characteristic table of D flip-flop is shown in Table 1. …Fundamentals of Digital Logic with VHDL Design Ch 8, Section EoC End of Chapter, Exercise 8.4The inputs are clock and reset.

The output is z and it consists of 4 bits. According to the states…Fundamentals of Digital Logic with VHDL Design Ch 9, Section EoC End of Chapter, Exercise 9.1Consider that w_{1} and w_{2} are the inputs, y_{1} and y_{2} are the next states, z_{1} and z_{2}…

Fundamentals of Digital Logic with VHDL Design Ch 10, Section EoC End of Chapter, Exercise 10.1The modified shift register circuit in which the parallel-load operation can be performed only when…Fundamentals of Digital Logic with VHDL Design INTRO TO DIGITAL LOGIC

ECEN 248 ECEN248 Lab 8 Introduction to Sequential Logic – Texas A&M

Tests Questions & Answers Showing 1 to 8 of 26 View all Please see attachments for details 1 2 3 4 5 Please see an attachment for details 1 2 3 4 5 Please see an attachment for details 1 2 3 4 5

Please see an attachment for details 1 2 3 4 5 The attached problems please 1 2 3 4 5 The three attached problems. 1 2 3 4 5 These are simplified equations using boolean algebra can you please help me optimize each one and draw the circuits please. 1 2 3 4 5 Can you please help me simplify each one separately using boolean algebra 1 2 3 4 5

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