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ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

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ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

Laboratory Exercise #12 The Traffic Light Controller Lab

1Introduction

The lab this week will continue the introduction to FSMs with a simple Traffic Light Controller designproject. In the pre-lab, you will have the opportunity to create a state diagram of aMealymachine, whichimplements a traffic light controller, based on provided guidelines.

You will then use this state diagramto write the behavioral Verilog description of the traffic light controller. The testing of your traffic lightcontroller will take place during the lab session using the ISE development tools and the Spartan 3E board.

As with the previous lab, we will make use of the character LCD screen to display the outputs of our digitalcircuit.

2Background

Background information necessary for the completion of this lab assignment will be presented in the nextfew subsection. The pre-lab assignment that follows will test your understanding of the background material.

2.1The Mealy Machine

Description

  

ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

Laboratory Exercise #12 The Traffic Light Controller Lab

1Introduction

The lab this week will continue the introduction to FSMs with a simple Traffic Light Controller designproject. In the pre-lab, you will have the opportunity to create a state diagram of aMealymachine, whichimplements a traffic light controller, based on provided guidelines.

You will then use this state diagramto write the behavioral Verilog description of the traffic light controller. The testing of your traffic lightcontroller will take place during the lab session using the ISE development tools and the Spartan 3E board.

As with the previous lab, we will make use of the character LCD screen to display the outputs of our digitalcircuit.

2Background

Background information necessary for the completion of this lab assignment will be presented in the nextfew subsection. The pre-lab assignment that follows will test your understanding of the background material.

2.1The Mealy Machine

As mentioned in the previous lab, theMealymachine is a Finite State Machine (FSM) in which the outputsof the machine are dependent not only on the state of the machine but also on the input to the machine.

As areminder, Figure 1 highlights the distinction between theMealyand the Moore machine with a simple blueline that connects the input to the next-state logic

As an example, consider the 2-bit saturating counter discussed previously. Let us suppose that we wereasked to add an additional output signal,Sat, that is asserted when the counter is saturated in either themaximum or minimum state.

Assuming that the counter is not considered to be in saturation when it firstenters the minimum or maximum state, but rather when it remains in either of those states, we would needto use the state andthe input of the machine to create this output signal. In terms of the state diagram,Sat

will need to be based on the state transitions of the machine as seen in Figure 2. Notice thatSatis definedon the transitions (i.e. edges of the graph) rather than on the states (i.e. nodes of the graph).

The behavioral Verilog for the modified 2-bit saturating counter is nearly identical to the previousdescription with the exception of an additionalalwaysblock, which describes the combinational logicused to generate theSatsignal.To make clear the dependenciesSathas on the state and input, thealways@(stateorUp) clause has been used.

It should be noted thatalways@(*) would have worked aswell.

1‘ t i m e s c a l e1 ns/2ns‘ d e f a u l tn e t t y p enone

3/*Thisi sab e h a v i o r a lV e r i l o gd e s c r i p t i o nof*

5*a 2b i ts a t u r a t i n gcounter .*/modules a t u r a t i n gc o u n t e r (

7/*o u t p u tandi n p u tarewires*/outputwire[ 1 : 0 ]Count ;/ / 2b i to u t p u t

9outputreg

ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

ECEN 248 INTRO TO DIGITAL LOGIC School: Texas A&M University (Texas A&M) *Professor:Ivan Diaz Rodriguez, Lu, CHOI, SRINIVAS, SHAKKOTTAI, Staff, K… Documents (2709) Q&A (26) Textbook Exercises (20+) Most important docs of the week 3 pagesLab 1 Post-Lab.docxLab 1 Post-Lab.docx Texas A&M University

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ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

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ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

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ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

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ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

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ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

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ECEN 248 – Spring 2016 Register Now PreLab 10.pdf Textbook Exercises Fundamentals of Digital Logic with VHDL Design image Fundamentals of Digital Logic with VHDL Design Ch 2, Section EoC End of Chapter, Exercise 2.1Consider the expression x+yz=(x+y)(x+z) .

Consider the left handed term is x+yz and the right…Fundamentals of Digital Logic with VHDL Design Ch 3, Section EoC End of Chapter, Exercise 3.1For a 3 input logic circuit, there are 8 different combinations for which the output can be…

ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

Fundamentals of Digital Logic with VHDL Design Ch 4, Section EoC End of Chapter, Exercise 4.1Write the truth table for the given function f(x_1,x_2,x_3)=\sum m(1,2,3,5) . Determine the number…Fundamentals of Digital Logic with VHDL Design Ch 5, Section EoC End of Chapter, Exercise 5.1

All positive numbers are called unsigned numbers. The binary number is represented by using the…Fundamentals of Digital Logic with VHDL Design Ch 6, Section EoC End of Chapter, Exercise 6.1Draw a 3 to 8 binary decoder for the given function, f(w_1, w_2, w_3)=\sum m(0, 2, 3, 4, 5, 7) .

It…Fundamentals of Digital Logic with VHDL Design Ch 7, Section EoC End of Chapter, Exercise 7.5Consider the characteristic table of D flip-flop is shown in Table 1. …Fundamentals of Digital Logic with VHDL Design Ch 8, Section EoC End of Chapter, Exercise 8.4The inputs are clock and reset.

The output is z and it consists of 4 bits. According to the states…Fundamentals of Digital Logic with VHDL Design Ch 9, Section EoC End of Chapter, Exercise 9.1Consider that w_{1} and w_{2} are the inputs, y_{1} and y_{2} are the next states, z_{1} and z_{2}…

Fundamentals of Digital Logic with VHDL Design Ch 10, Section EoC End of Chapter, Exercise 10.1The modified shift register circuit in which the parallel-load operation can be performed only when…Fundamentals of Digital Logic with VHDL Design INTRO TO DIGITAL LOGIC

ECEN 248 ECEN248 Laboratory Exercise#12 – Texas A&M

Tests Questions & Answers Showing 1 to 8 of 26 View all Please see attachments for details 1 2 3 4 5 Please see an attachment for details 1 2 3 4 5 Please see an attachment for details 1 2 3 4 5

Please see an attachment for details 1 2 3 4 5 The attached problems please 1 2 3 4 5 The three attached problems. 1 2 3 4 5 These are simplified equations using boolean algebra can you please help me optimize each one and draw the circuits please. 1 2 3 4 5 Can you please help me simplify each one separately using boolean algebra 1 2 3 4 5

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